- DesignWare IP portfolio for GLOBALFOUNDRIES 12LP FinFET process includes Multi-Protocol 25G, USB 3.0 and 2.0, PCI Express 2.0, DDR4, LPDDR4/4X, MIPI D-PHY, SD-eMMC, and Data Converters
- Synopsys’ DesignWare IP are optimized for high performance and low latency in compute-intensive applications, such as artificial intelligence, high-end smartphones, and networking infrastructure
- Long-standing collaboration between the two companies has resulted in the successful development of DesignWare IP from 180-nm to 12-nm
Synopsys, Inc. (Nasdaq: SNPS) today announced its collaboration with GLOBALFOUNDRIES (GF) to develop a broad portfolio of DesignWare® IP, including Multi-Protocol 25G, USB 3.0 and 2.0, PCI Express® 2.0, DDR4, LPDDR4/4X, MIPI D-PHY, SD-eMMC, and Data Converters, for GF’s 12-nanometer (nm) Leading-Performance (12LP) FinFET process technology. Synopsys’ DesignWare IP on the GF 12LP process enables designers to implement the latest interface and analog IP solutions in their artificial intelligence (AI), cloud computing, mobile, and consumer system-on-chips (SoCs) on GF’s 12LP technology, which delivers a 10 percent improvement in logic density and more than a 15 percent improvement in performance compared to previous FinFET generations. This collaboration is another extension to the long-standing relationship between the two companies, which has delivered DesignWare IP for GF’s processes from 180-nm to 12-nm.
“In response to growing demand for differentiated, feature-rich FinFET offerings, we are collaborating with Synopsys to provide quality IP in GF’s processes, enabling designers to deliver differentiated products to a broad set of market segments,” said Mark Ireland, vice president of Ecosystem Partnerships at GF. “The combination of our 12LP process with 3D FinFET transistor technology and Synopsys’ high-performance DesignWare IP allows our mutual customers to accelerate their time to volume production.”
“As the leading provider of interface IP, Synopsys continues to collaborate with key foundries, such as GF, to deliver DesignWare IP solutions for the latest FinFET process technologies,” said John Koeter, vice president of marketing for IP at Synopsys. “With Synopsys’ DesignWare IP portfolio in GF’s 12LP process, designers can efficiently integrate the necessary functionality into their complex SoCs while meeting the bandwidth and power requirements of their mobile and high-end computing applications.”
SOURCE Synopsys, Inc.